1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a layered wiring structure.
2. Description of the Background Art
For the wirings of a power supply for a semiconductor device, it is usual to give a large wiring width in order to enhance a noise resistance. On the other hand, if a large wiring width is provided for signal wirings of a semiconductor device, the lowering of a switching speed take places owing to the increase in wiring capacitance, along with an increasing layout area. To avoid this, it is desirable that the width of signal wirings be minimized within a range where a required wiring resistance is satisfied and migration can be appropriately prevented.
As for the signal wirings, there is the tendency toward the formation of a finer wiring and a thinner film owing to the development of a high integration technique or a microfabrication technique. In contrast, with respect to the wirings for power supply, a difficulty is involved in ensuring more microfabrication while keeping a required performance. Hence, it becomes necessary in recent years to form a wiring for signal and a wiring for power supply in separate layers. This is one of factors standing in the way of the microfabrication of a semiconductor device and the reduction in cost.
As a technique of solving the above-stated problems, there are known a manufacturing method disclosed, for example, in Japanese Patent Laid-open No. Hei 2-264432 (hereinafter referred to as xe2x80x9cfirst prior art methodxe2x80x9d) and a manufacturing method disclosed in Japanese Patent Laid-open No. Hei 4-372133 (hereinafter referred to as xe2x80x9csecond prior art methodxe2x80x9d).
FIGS. 8A through 8D are sectional views for illustrating the first prior art method. In these Figures, indicated at 111 is a semiconductor substrate, at 112 is an interlayer film, at 113 is a metal wiring material, at 114 is a first resist and at 115 is a second resist.
In the first prior art method, the metal wiring material 113 is deposited on the interlayer film 112 in a film thickness of a thick film wiring as is particularly shown in FIG. 8A.
Next, as shown in FIG. 8B, the first resist 114 is formed to cover only a portion where a thick film wiring is to be formed. The exposed portion of the metal wiring material 113 is etched by anisotropic etching through the first resist 114 as a mask to a given film thickness, particularly, to a film thickness to be given to a thin film wiring.
Next, as shown in FIG. 8C, the second resist 115 is formed on the metal wiring material 113 so as to cover sites where a thick film wiring is to be formed and where a thin film wiring is to be formed. Then, anisotropic etching is again performed through the second resist 115 as a mask.
As shown in FIG. 8D, the second resist 115 is removed from the metal wiring material 113 to form the thick film wiring and the thin film wiring. Thus, according to the first prior art method, two types of wirings having significantly different film thicknesses can be formed in the same layer.
FIG. 9 shows sectional views illustrating the second prior art method. In FIG. 9, indicated by 201 is a semiconductor substrate, 202 is an inter-layer insulating film, 203 is an aluminum layer, 204 is a resist for the formation of a thick film wiring, 205 is a resist for the formation of a thin film wiring, 206 is a thin film wiring, and 207 is a thick film wiring.
In the second prior art method, the aluminum layer 203 is first deposited on the inter-layer insulating film 202 by sputtering in a thickness of 2 to 3 xcexcm as shown in FIG. 9A. Then, the resist 204 for thick film wiring is formed on the aluminum layer 203.
As shown in FIG. 9B, anisotropic etching is effected through a mask of the resist 204 to make the film thickness of the aluminum layer 203 at approximately 1 xcexcm. Thereafter, the resist 204 is thermally shrunk for curing.
As shown in FIG. 9C, the resist 205 for thin film wiring is formed so as to cover the surface of the thermally shrunk resist 204 and the surface of the aluminum layer 203.
Next, as shown in FIG. 9D, the reticle having a pattern for thin film wiring is used to pattern the resist 205. The resist 204 for thick film wiring leaves on the aluminum layer 203 after development of the resist 205 since being cured.
Next, as shown in FIG. 9E, the aluminum layer 203 is etched according to anisotropic etching wherein the resists 204 and 205 are used as a mask. The resists 204, 205 are removed according to a plasma method after completion of the etching. As a consequence, there are formed, in the same layer, the thick film wiring 207 having a large wiring width and film thickness and the thin film wiring 206 having a small wiring width and film thickness. In this way, according to the second prior art method, there can be formed, in the same layer, two types of wirings having different film thicknesses, respectively.
However, in the above-stated first prior art method, it becomes necessary to form the second resist on the metal wiring material 113 after patterning the thick film wiring halfway using the first resist 114 as a mask. In this case, it is very difficult to form the second resist 115 on the site where the thin film wiring is to be formed, i.e. on the site which is patterned halfway, in high precision. Accordingly, the first prior art method has the problem that it does not stably proceed at the time of mass-production.
On the other hand, the second prior art method involves a change in shape of the resist 204 prior to and after the thermal shrinkage. This makes it difficult to form the thick film wiring in high precision according to the second prior art method. Moreover, it is difficult to completely remove the resist 204 cured by thermal shrinkage by the plasma method. Accordingly, the second prior art method has the problem that a residue is liable to occur on the thick film wiring 207.
The invention has been accomplished in order to solve such problems as set out above and has for its object the provision of a semiconductor device, which has plural types of wirings having different thicknesses from one another in one layer and which is excellent in mass-production stability and has such a structure that is unlikely to cause a residue to be left on the wirings.
The above objects of the present invention are achieved by a semiconductor device described below. The semiconductor device includes a thick film wiring having a first film thickness as well as a thin film wiring having a second film thickness that is smaller than the first film thickness. The thick film wiring and the thin film wiring are formed in a single layer. The surface of the thick film is covered with a hard mask. The hard mask is resistant to etching adapted for patterning of the thick film wiring and also to etching adapted for patterning of the thin film wiring, while being resistant to heat.
The above objects of the present invention are also achieved by a semiconductor device described below. The semiconductor device includes a thick film wiring having a first film thickness as well as a thin film wiring having a second film thickness that is smaller than the first film thickness. The thick film wiring and the thin film wiring are formed in a single layer. A metallic anti-reflective film covers the surface of the thin film wiring.
The above objects of the present invention are further achieved by a semiconductor device described below. The semiconductor includes a thick film wiring having a first film thickness as well as a thin film wiring having a second film thickness that is smaller than the first film thickness. The thick film wiring and the thin film wiring are formed in a single layer. The semiconductor device also includes an inter-layer insulating film surrounding the thick film wiring and covering the thin film wiring. The thick film wiring also serves as a plug which functions as a plug capable of connection with a wiring layer formed as an upper layer on the inter-layer insulating film.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.